Socionext's first Intel 18A-P project is a high-performance compute chiplet
A design-start commitment, not a datapoint on 18A-P yield — but the chiplet framing says which parts of Intel's stack are being bought.
Socionext announced on August 18, 2026, from Yokohama and Milpitas, that it will use Intel 18A-P process technology to develop custom SoCs for datacenter, edge, and high-performance computing customers. The release names one concrete deliverable: the first development is a high-performance compute chiplet.
That single sentence is the whole verifiable core of the announcement, and it is worth more than the rest of the release.
What was actually said
Socionext is an ASIC house — it builds custom silicon to a customer's specification rather than selling its own catalog parts. The release frames the arrangement as combining that methodology with Intel Foundry's process and packaging roadmap.
The combination of Socionext's Solution SoC development methodology and Intel Foundry's advanced process and packaging technologies enriches the ecosystem for enabling product development for AI acceleration, high-performance compute, and Physical AI.
John Zucker, General Manager and VP of Global Business Development and Marketing, Intel Foundry
Socionext's CTO and Executive Vice President, Rajinder Cheema, is quoted on the node itself: "Intel 18A-P represents an important step in advanced process technology, combining innovations in transistor architecture and power delivery."
Note what that quote does and does not say. It characterizes 18A-P in terms of transistor architecture and power delivery — gate-all-around and backside power, the two structural changes in the 18A family — without asserting a performance or density comparison against anything.
No numbers, and that is the notable part
The release discloses no performance figures, no density figures, no power figures, no wafer volumes, no tape-out date, and no customer for the compute chiplet.
For a foundry announcement that is unremarkable — process comparisons are usually under NDA and PDK access predates any silicon anyone can measure. But it does bound what a reader can conclude. This is a design-start commitment, not evidence about 18A-P yield or performance. Anyone reading it as a datapoint on how 18A-P is going is reading in something the document does not contain.
What the document does establish is that an external ASIC vendor has committed engineering effort to Intel Foundry's leading-edge node for a compute chiplet — a category where the customer is buying transistors that have to compete on performance per watt, not transistors that merely have to work.
Why the chiplet framing matters
A chiplet is a lower-risk first project than a monolithic SoC, and it is a better fit for what Intel is selling. Intel's own Hot Chips material four days earlier described the same 18A-P node carrying Diamond Rapids, its next-generation Xeon, and named Foveros Direct 3D packaging and UCIe as enabling technologies across its slate.
That is the shape of the offer: a node plus an advanced packaging stack plus a standard die-to-die interface. An ASIC vendor whose first project is a compute chiplet is buying into all three, not just the transistors. It also means the project can be judged on its own die rather than on a full-reticle SoC where a single blocking issue anywhere kills the schedule.
The open question the release leaves is timing. There is no date attached to the compute chiplet, and no indication of whether the first customer product is silicon in 2027 or later. Until one of those appears, this is a roadmap commitment with two named executives behind it — which is more than a press release usually carries, and less than a shipping part.
Primary sources: Socionext, "Socionext Broadens SoC Roadmap with Intel 18A-P Process Technology", Intel Newsroom, "Intel Outlines Architectures for Agentic AI at Hot Chips 2026", read 2026-08-28.